Programmable read-only memory device

ABSTRACT

A PROM device having the improved bit address decoders composed of a plurality of AND gates, each of the AND gates comprising PNP type transistors, to each base of which is applied an address signal from the bit address inverters. Each collector of these transistors is connected to ground, and each emitter is connected to the output terminal of the bit address decoder.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a programmable read-only memory device,and more particularly to a bipolar semiconductor programmable read-onlymemory device having improved bit address decoder circuits, used inelectronic equipment such as an electronic computer.

(2) Description of the Prior Art

In general, a programmable read only memory (PROM) device comprises aplurality of memory cells disposed at each cross position of the matrixwhich is formed by a intersection of a plurality of bit lines and aplurality of word lines. Each of the memory cells is, for example, ashorted-junction type or a fuse-blown type cell, and is connectedbetween one of the word lines and one of the bit lines. The PROM devicealso comprises address buffers or address inverters which amplify andinvert input address signals, decoders which decode the address signalsfrom the address buffers, multiplexers or encoders which encodeinformation from the memory cells, output buffers which amplify outputsignals from the multiplexers, and program circuits or writing-incircuits which initially write in information to the selected memorycell.

In the prior art PROM device, several kinds of decoders are usedincluding a word address decoder for decoding word address signals inorder to select one of the word lines, and bit address decoders fordecoding bit address signals in order to select one of the bit lines.The bit address decoder of one kind is connected to the multiplexer andis used for reading-out of information from the selected memory cell,and the bit address decoder of the other kind is connected to theprogram circuit and is used for writing-in of information to theselected memory cell. These two kinds of bit address decoders aresupplied with the same bit address signals. Each of the bit addressdecoders is composed of a plurality of AND gates, each of which consistsof a plurality of diodes. Therefore, the sink current, which flows fromthe program circuit or multiplexer through the diodes to the bit addressinverters, is relatively large. Consequently, it is necessary to useoutput power transistors having a large driving capability in the outputstage of the bit address inverters, and it is also necessary to usedifferent inverters for driving the two kinds of decoders.

In order to gain a large driving capability in the prior art PROM devicethe size of the output power transistors of the bit address invertersmust be large, so that the packing density of the PROM device is reducedand the switching speed of the bit address inverters becomes low.Moreover, the prior art PROM device needs different bit addressinverters for driving the two decoders, which also leads to a lowpacking density of the PROM device.

SUMMARY OF THE INVENTION

It is an object of the present invention to gain a high switching speedof the bit address inverters by decreasing the current which flows intothe output stage of the bit address inverters when writing-in orreading-out of information is performed.

It is another object of the present invention to simplify the circuitryof the bit address inverters by using common bit address inverters fordriving both the decoders, in the reading-out stage and in thewriting-in stage.

These objects of the present invention are attained by providing thePROM device with bit address decoder circuits composed of a plurality ofAND gates. Each of the AND gates includes a plurality of PNP typetransistors, to each base electrode of which is applied the addresssignals from the bit address interters. Each collector electrode isconnected commonly to the ground, and each emitter electrode isconnected commonly as an output terminal of the bit address decodercircuit.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional bipolar 4 K-bit PROM device.

FIG. 2 is a partial block circuit diagram of a prior art PROM devicehaving bit address decoders consisting of a plurality of diode ANDgates.

FIG. 3 is a partial block circuit diagram illustrating a part of a PROMdevice in an embodiment of the present invention, in which bit addressdecoders comprise a plurality of AND gates composed of PNP transistors.

FIG. 4 is a circuit diagram of the bit address inverters used in thePROM device of FIG. 3.

FIG. 5 is a circuit diagram of a word address decoder/driver circuitused in the PROM device of FIG. 3.

FIG. 6 is a circuit diagram of a program circuit unit as used in thePROM device of FIG. 3.

FIG. 7 is a circuit diagram illustrating a multiplexer unit and anoutput buffer unit used in the PROM device of FIG. 3.

FIG. 8 is a partial block diagram of a part of a PROM device in anotherembodiment of the present invention, with simplified bit addressbuffers.

DETAILED DESCRIPTION OF THE INVENTION [Prior Art]

FIG. 1 is a block diagram of a conventional bipolar 4 K-bit PROM device,which comprises a memory cell array 2 composed of 4096 memory cellsdisposed in a matrix of 64 rows and 64 columns. Each of the memory cellsis composed, for example, of an open-base type transistor which isequivalent to a series connection of two diodes of opposite polarity.The writing-in of information to this memory cell is effected byshort-circuiting one of the PN junctions by application of a largewriting-in current. A word address buffer or word address inverters 4amplify and invert input word address signals A₀ through A₅, and theword address decoder/driver 6 decodes the word address signals from theword address buffer 4 and applies the decoded word address signals tothe memory cell array 2. The bit address buffer or bit address inverters8 amplify and invert input bit address signals A₆ through A₉, and applythe output bit address signals to the bit address decoder 10 connectedto the multiplexer 14, and to the bit address decoder 12 connected tothe program circuit 20. The decoder 10 decodes the output bit addresssignals from the bit address buffer 8 and applies the decoded bitaddress signals (bit selection signals for reading-out) to themultiplexer 14. The multiplexer 14 reads out information from the memorycells connected between the word line selected by the above-mentionedword address decoder/driver 6 and the bit lines selected by the bitaddress decoder 10. The output buffer 16 amplifies the reading outsignals from the multiplexer 14, and applies the amplified reading outsignals to output terminals OP₁ through OP₄. The output buffer 16 isenabled by the chip enable circuit 18 which receives an input chipenable signal. The decoder 12 decodes the output bit address signalsfrom the bit address buffer 8 and applies the decoded bit addresssignals (bit address signals for writing-in) to the program circuit 20.The program circuit 20 writes in information to the memory cells whichare connected between the word line selected by the word addressdecoder/driver 6 and the bit lines selected by the bit address decoder12.

The reading out of information from the above-mentioned PROM is effectedby applying the 6 bit word address signals A₀ through A₅ to the wordaddress buffer 4, the 4-bit bit address signals A₆ through A₉ to the bitaddress buffer 8, and a "low" level voltage to the chip enable circuit18. 4 bits of information from the selected memory cells appears at theoutput terminals OP₁ through OP₄, through the multiplexer 14 and theoutput buffer 16.

The writing-in of information to the PROM is effected by applying the6-bit word address signals A₀ through A₅ to the word address buffer 4,the 4-bit bit address signals A₆ through A₉ to the bit address buffer 8,and the "high" level voltage to the chip enable circuit 18. The 4-bitdata signals to be written-in are applied to the output terminals OP₁through OP₄ of the PROM device. In this case, the output buffer 16 iscut off from the output terminals OP₁ through OP₄ due to the "high"level signal to the chip enable circuit 18. Therefore, the data signalsto be written-in pass from the output terminal to the program circuit20, and the writing-in of information corresponding to the data signalsto the selected memory cells is effected.

FIG. 2 is a partial block diagram illustrating a conventional PROMdevice having bit address decoders consisting of a plurality of diodeAND gates. In FIG. 2, the bit address buffer unit BB₆ consists of aseries connection of four inverters INV₁ through INV₄. An input terminal22 of the inverter INV₁ serves as the input terminal of the bit addressbuffer BB₆. Output terminals of the inverters INV₁ and INV₂ areconnected to the corresponding leads of the address signal lines 26 inthe reading-out stage, and output terminals of the inverters INV₃ andINV₄ are connected to the corresponding leads of the address signallines 24 in the writing-in stage. In addition to the bit address bufferunit BB₆, there are three other bit address buffer units BB₇ through BB₉connected to the bit address signal lines 24 and 26, which are not shownin the drawing. Bit address decoder units or AND gates G₁ and G₂ areconnected respectively to the address signal lines 24 and 26. Inaddition to the AND gates G₁ and G₂, there are fifteen other AND gatesconnected to the address signal lines 24 and fifteen other AND gatesconnected to the address signal lines 26, which are not shown in thedrawing. Output terminals T₁ and T₂ of the AND gates G₁ and G₂ areconnected to the program circuit or the writing-in circuit 20 and to themultiplexer or the reading-out circuit 14 respectively. A terminal T₃ ofthe program circuit 20 is connected to one end of a bit line B_(i), towhich the emitter of the memory cell transistor Q_(c) is connected. Thecollector of the memory cell transistor Q_(c) is connected to a wordline W_(i) which is connected to an output terminal of the word addressdecoder/driver circuit 6. The other end of the bit line B_(i) isconnected to a bit line terminal T₄ of the multiplexer 14. An outputterminal T₅ of the output buffer 16 is connected to a writing-in currentinput terminal of the program circuit 20.

Operation of the circuit illustrated in FIG. 2 will now be explained.The input bit address signal, for example, A₆ is applied to the addresssignal input terminal 22, and the address signals A₆ and A₆ are producedby the inverters INV₁ through INV₄ and supplied to the address signallines 24 and 26. The input bit address signals consist of four bitsignals A₆ through A₉. Therefore, the other three bit address signalsA₇, A₈, and A₉ are applied to the other inverter stages, which are notshown in the drawing, and the address signals A₇, A₇, A₈, A₈, A₉, and A₉are produced and supplied to the corresponding lines of the addresssignal lines 24 and 26.

The address signals from the address signal lines 24 and 26 arerespectively supplied to the writing-in circuit 20 and the reading-outcircuit 14 through the AND gates (decoder units) G₁ and G₂ and decoderoutput terminals T₁ and T₂.

The AND gates G₁ and G₂ each consist of four diodes D₁ through D₄ and D₅through D₈ respectively. Each anode electrode of the diodes D₁ throughD₄ is connected commonly to the decoder output terminal T₁, and eachanode electrode of the diodes D₅ through D₈ is connected commonly to thedecoder output terminal T₂. The cathode electrodes of the diodes D₁through D₄ are connected, for example, to the leads A₆, A₇, A₈, and A₉,respectively, of the address signal lines 24, and the cathode electrodesof the diodes D₅ through D₈ are connected to the corresponding leads A₆,A₇, A₈, and A₉, respectively, of the address signal lines 26.

If one or more of the address signals A₆, A₇, A₈, A₉, appliedrespectively to the diodes D₁, D₂, D₃, and D₄, which compose the ANDgate G₁, is "low", the output signal from the AND gate G₁ goes "low" sothat the writing-in circuit 20 is not enabled. If all of the addresssignals A₆, A₇, A₈, and A₉ are "high", the output signal of the AND gateG₁ becomes high and current does not flow from the writing-in circuit 20to the AND gate G₁ so that the writing-in circuit is enabled.

The writing-in circuit 20, which is enabled by the address signals A₆,A₇, A₈, and A₉, passes the writing-in current supplied from the outputterminal T₅ through the terminal T₃ to the bit line B_(i) correspondingto the address signals.

The emitter-base junction of the memory cell transistor Q_(c), which isconnected between the above-mentioned bit line B_(i) and the word lineselected by the word address decoder/driver circuit 6, is shortcircuited due to the writing-in current; thereby the writing-in ofinformation is performed.

With regard to the reading-out of information, when all of the addresssignals A₆, A₇, A₈, and A₉ are "high", the output of the AND gate G₂becomes "high", and the AND gate G₂ does not absorb current from thereading-out circuit 14, so that the reading-out circuit 14 is enabledand the reading-out of information from the corresponding bit line B_(i)is performed.

If the memory cell transistor Q_(c) connected between the bit line B_(i)and the word line W_(i) selected by the word address decoder/drivercircuit 6 is short-circuited at its emitter-base junction, thereading-out current flows from the terminal T₄ through the bit lineB_(i), the cell transistor Q_(c), and the word line W_(i), to the wordaddress decoder/driver circuit 6. If the memory cell transistor Q_(c) isnot short circuited, the reading-out current does not flow.

The reading-out circuit 14 detects the information from the memory cellQ_(c) by detecting whether the above-mentioned reading-out current flowsor not, and outputs the detected information from the output terminalT₅.

In this case, the selected word line W_(i) is pulled down to "low" bythe word address decoder/driver circuit 6; thereby the writing-incurrent or reading-out current can be absorbed by the circuit 6.

However, since each of the AND gates G₁ and G₂ of the circuitillustrated in FIG. 1 consists of diodes, the current which passes fromthe writing-in circuit 20 or the reading-out circuit 14 to the outputstages of the bit address inverters INV₁ through INV₄ becomes relativelylarge, so that it is necessary to use transistors having a large currentdriving capability for the output transistors of the inverters INV₁through INV₄.

In order to gain a large current driving capability, large transistorsmust be used in the output stage of the bit address inverters, so thatthe packing density of the PROM device is decreased and the operatingspeed of the inverters becomes low due to the increase of parasiticcapacitance.

In the above-mentioned PROM device, the current flowing from thewriting-in circuit 20 to the output stage of the inverters is severaltimes as large as the current flowing from the reading-out circuit 14 tothe output stage of the inverters. Therefore, the address signalssupplied to the writing-in stage and the address signals supplied to thereading-out stage are produced by the different inverters.

[Preferred Embodiments of the Present Invention]

With reference to FIG. 3, an embodiment of the present invention willnow be described. A circuit shown in FIG. 3 includes improved bitaddress decoder units G'₁ and G'₂ which replace the decoder units G₁ andG₂ shown in FIG. 2. Each decoder unit G'₁ or G'₂ consists of four PNPtype transistors, Q₁ through Q₄ or Q₅ through Q₈, instead of the diodes,D₁ through D₄ of the decoder G₁ or D₅ through D₈, of the decoder G₂included in the circuit of FIG. 2. Each base electrode of thetransistors Q₁ through Q₄ or Q₅ through Q₈ is connected to the addresssignal lines 24 or 26, each collector electrode is commonly connected tothe ground, and each emitter electrode is commonly connected to thedecoder output terminal T₁ or T₂. The other part of the circuit of FIG.3 is the same as that of the circuit illustrated in FIG. 2, and thedescription thereof is omitted herein.

Operation of the improved decoder unit will now be described. When atleast one of the address signals A₆, A₇, A₈, or A₉ from the addresssignal lines 24 or 26 is "low", at least one of the transistors Q₁through Q₄ or Q₅ through Q₈ turns on, and current I flows from thedecoder output terminal T₁ or T₂ to the emitter electrode of one or moreof the turned on transistors. Assuming that only one PNP transistor Q₁is turned on, the above-mentioned current I passes from the emitterelectrode of the transistor Q₁ to the base electrode and the collectorelectrode. In this case, almost all of the current I passes through thecollector electrode to the ground, and the base current I(1-α) which isdetermined by the current amplification factor α is very small. Forexample, if α=0.98, then the base current is equal to I/50. Therefore,the current passing from the address signal lines 24 and 26 to theoutput stage of the bit address inverters INV₁ through INV₄ is greatlydecreased, so that the size of each output transistor of the inverterscan be decreased and a high operating speed of the inverters can beattained.

FIG. 4 illustrates a detailed circuit of the bit address buffer BB₆,which is a series connection of four inverters INV₁ through INV₄. InFIG. 4, the input terminal 22 of the bit address buffer is connected tothe emitter electrode of NPN type transistor Q₄₀, and is connected tothe ground through the diode D₄₀. The base electrode of the transistorQ₄₀ is connected to a positive voltage source V_(cc) through resistorR₄₀, and the collector electrode of the transistor Q₄₀ is connected tothe base electrode of NPN type transistor Q₄₁. The collector electrodeof the transistor Q₄₁ is connected to the base electrode of NPN typetransistor Q₄₂, and to the voltage source V_(cc) through resistor R₄₁.The emitter electrode of the transistor Q₄₁ is connected to the baseelectrode of NPN type transistor Q₄₃, and to the ground through resistorR₄₂. The collector electrode of the transistor Q₄₂ is connected to thevoltage source through resistor R₄₃. The emitter electrode of thetransistor Q₄₂ is connected to output terminal of the first inverterINV₁, and to the collector electrode of the transistor Q₄₃ through diodeD₄₁. The collector electrode of the transistor Q₄₃ is connected to aninput terminal of the second inverter INV₂, i.e. the emitter electrodeof NPN type transistor Q₄₄. The structure of the second inverter circuitINV₂ is the same as that of the first inverter INV₁, except that thesecond inverter INV₂ does not contain a diode corresponding to the diodeD₄₀ of the first inverter. The third inverter INV₃ consists of three NPNtype transistors Q₄₈ through Q₄₁₀ and three resistors R₄₈ through R₄₁₀.The emitter electrode of the transistor Q₄₈ is connected to thecollector electrode of transistor Q₄₇. The base electrode of thetransistor Q₄₈ is connected to the voltage source V_(cc) through theresistor R₄₈. The collector electrode of the transistor Q₄₈ is connectedto the base electrode of the transistor Q₄₉. The collector electrode ofthe transistor Q₄₉ is connected to the voltage source V_(cc) through theresistor R₄₉. The emitter electrode of the transistor Q₄₉ is connectedto the base electrode of the transistor Q₄₁₀, and to the ground throughthe resistor R₄₁₀. The collector electrode of the transistor Q₄₁₀constitutes an output terminal of the third inverter INV₃. The emitterelectrode of the transistor Q₄₁₀ is connected to the ground. The fourthinverter INV₄ consists of two NPN type transistors Q₄₁₁ and Q₄₁₂, twodiodes D₄₃, D₄₄, and three resistors R₄₁₁ through R₄₁₃. The cathodeelectrode of the diode D₄₃ constitutes an input terminal of the fourthinverter INV₄, and is connected to the collector electrode of thetransistor Q₄₁₀. The anode electrodes of the diodes D₄₃ and D₄₄ areconnected to each other, and to the voltage source V_(cc) throughresistor R₄₁₁. The cathode electrode of the diode D₄₄ is connected tothe base electrode of the transistor Q₄₁₁. The collector electrode ofQ₄₁₁ is connected to the voltage source V_(cc) through the resistorR₄₁₂. The emitter electrode of the transistor Q₄₁₁ is connected to thebase electrode of the transistor Q₄₁₂, and to the ground through theresistor R₄₁₃. The emitter electrode of the transistor Q₄₁₂ is connectedto the ground, and the collector electrode of the transistor Q₄₁₂constitutes an output terminal of the bit address buffer.

Operation of the circuit in FIG. 4 will now be described. Assume that a"low" voltage is applied to the input terminal 22, in which conditionthe transistor Q₄₀ turns on and the collector voltage of the transistorQ₄₀ becomes "low", thereby turning off the transistor Q₄₁. When thetransistor Q₄₁ so turns off, no current flows from the collector to theemitter of the transistor Q₄₁. Therefore, no current flows through theresistor R₄₂, and the emitter voltage of the transistor Q₄₁ becomes"low" so that the transistor Q₄₃ turns off. In this condition, currentflows from the voltage source V_(cc) through the resistor R₄₁ to thebase electrode of the transistor Q₄₂, and the transistor Q₄₂ turns on,so that the emitter electrode of the transistor Q₄₂ or the outputterminal of the first inverter INV₁ becomes "high". If a "high" voltageis applied to the input terminal 22, no current flows from the voltagesource V_(cc) through the resistor R₄₀ to the emitter electrode of thetransistor Q₄₀, so that the transistor Q₄₀ turns off, and current flowsfrom the voltage source V_(cc) through the resistor R₄₀ and thebase-collector junction of the transistor Q₄₀ to the base electrode ofthe transistor Q₄₁. Consequently, the transistor Q₄₁ turns on, andcurrent flows from the voltage source V_(cc) through the resistor R₄₁,through the collector-emitter current path of Q₄₁ and through theresistor R₄₂ to the ground. Therefore, the voltage of the emitterelectrode of the transistor Q₄₁ becomes higher than the forward biasedvoltage drop of the base-emitter junction of the transistor Q₄₃, and thetransistor Q₄₃ turns on. When the transistor Q₄₃ so turns on, thecollector voltage of the transistor Q₄₃ becomes "low" and current flowsfrom the output terminal through the diode D₄₁ and the collectorelectrode of the transistor Q₄₃. In this condition, the emitter voltageof the transistor Q₄₂ is the sum of the forward voltage (about 0.8 volt)of the diode D₄₁ and the collector-emitter saturation voltage (about 0.2volt), of transistor Q₄₃, and the base voltage of the transistor Q₄₂ isthe sum of the collector-emitter saturation voltage (about 0.2 volt) ofthe transistor Q₄₁ and the forward voltage of the base-emitter junctionof the transistor Q₄₃ (about 0.8 volt). Therefore, the base voltage andthe emitter voltage of the transistor Q₄₂ are substantially the same, sothat the transistor Q₄₂ turns off. The diode D₄₀ is used for absorbingthe undershoot current through the input terminal 22 in order to protectthe inverter circuit INV₁.

Operation of the second inverter INV₂ is the same as that of the firstinverter INV₁, and the explanation thereof is omitted herein.

The third inverter INV₃ operates as follows. Assume that the emittervoltage of the transistor Q₄₈ is "low", in which condition thetransistor Q₄₈ is turned on and the transistor Q₄₉ is turned off.Therefore, the emitter voltage of Q₄₉ is the same as that of the ground,and the transistor Q₄₁₀ is turned off so that the collector of thetransistor Q₄₁₀, i.e. the output of the third inverter INV₃, becomes"high". If the emitter voltage of the transistor Q₄₈ is "high", thetransistor Q₄₈ is turned off, and the base current of the transistor Q₄₉flows from the voltage source V_(cc) through the resistor R₄₈ and thebase-collector junction of the transistor Q₄₈, so that the transistorQ₄₉ is turned on. In response to the turn-on of the transistor Q₄₉, thetransistor Q₄₁₀ turns on and outputs the low level signal from itscollector electrode.

The fourth inverter INV₄ operates as follows. Assume that a "low" levelsignal is applied to the cathode of the diode D₄₃, in which conditionthe current flows from the voltage source V_(cc) through the resistorR₄₁₁ and the diode D₄₃. Therefore, the voltage of the common connectionpoint of the anode electrode of the diodes D₄₃ and D₄₄ and one terminalof the resistor R₄₁₁ is pulled down to "low", so that the transistorQ₄₁₁ turns off. Consequently, the transistor Q₄₁₂ turns off and outputsa "high" level signal from the collector thereof. If a "high" levelsignal is applied to the cathode of the diode D₄₃, current flows fromthe voltage source V_(cc) through the resistor R₄₁₁ and the diode D₄₄ tothe base electrode of the transistor Q₄₁₁, so that the transistor Q₄₁₁turns on. Therefore, current flows from the voltage source V_(cc)through the resistor R₄₁₂, the collector-emitter junction of thetransistor Q₄₁₁, and the resistor R₄₁₃ to the ground, and the emittervoltage of the transistor Q₄₁₁ becomes high. Consequently, thetransistor Q₄₁₂ turns on and outputs a low level signal from thecollector electrode thereof.

It should be noted that the third inverter INV₃ and the fourth inverterINV₄ do not contain output transistors corresponding to the transistorQ₄₂ of the first inverter INV₁, and the input circuit of the fourthinverter INV₄ is composed of the diodes D₄₃ and D₄₄ and the resistorR₄₁₁. This is because it is necessary to protect the inverters INV₃ andINV₄ from breaking down when the high voltage writing-in signal isapplied to the output terminals of the inverters INV₃ and INV₄ from theprogram circuit 20.

FIG. 5 is a circuit diagram illustrating the word address decoder/drivercircuit used in the embodiment of the PROM described above. In FIG. 5,the word address buffer 4 consists of six word address buffer units WB₀through WB₅, each of which consists of two inverters in series, INV₀₀and INV₀₁ through INV₅₀ and INV₅₁ respectively. Output terminals of theinverters INV₀₀, INV₀₁ through INV₅₀, INV₅₁ are connected to thecorresponding two leads of word address signal lines 50. The wordaddress decoder/driver circuit 6 consists of 64 word addressdecoder/driver units WD₀ through WD₆₃, whose output terminals areconnected to the corresponding word lines W₀ through W₆₃ of the memorycell array. Each decoder/driver unit, for example WD₀, comprise amulti-emitter transistor Q₅₀, three NPN type transistors Q₅₁, Q₅₂, andQ₅₃, a diode D₅₀ connected between collectors of the transistors Q₅₁ andQ₅₃, and five resistors R₅₀ through R₅₄. Emitters of the multi-emittertransistor Q₅₀ are selectively connected to the leads of the wordaddress signal lines 50. For example, in the word address decoder/driverunit WD₀ whose output is connected to the word line W₀, the emitters ofthe transistor Q₅₀ are connected to the leads A₀, A₁, A₂, A₃, A₄, andA₅, respectively.

Operation of a decoder/driver unit, for example WD₀, will now bedescribed. Assume that the input word address signals A₀ through A₅ areall "low", in which condition the voltage levels of the address signalleads A₀, A₁, A₂, A₃, A₄, and A₅ are all "high", and the multi-emittertransistor Q₅₀ turns off. Therefore, current flows from the positivevoltage source V_(cc) through the resistor R₅₀ to the base of thetransistor Q₅₁, so that the transistor Q₅₁ turns on. In response to theturning on of the transistor Q₅₁, the transistors Q₅₂ and Q₅₃ turn on,and the word line W₀ is pulled down to a "low" voltage level, whichmeans the selection of the word line W₀.

The diode D₅₀ is used to decrease the base current of the transistorsQ₅₁ through Q₅₃ and sustain the transistor Q₅₁ in an unsaturatedcondition in the reading-out mode, in order to gain a high operatingspeed. The diode D₅₀ is cut off in the writing-in mode, because thewriting-in current at high voltage is supplied from the writing-incircuit through the selected bit line and the selected memory cell tothe word line W₀. In the reading-out mode, the diode D₅₀ turns on andthe collection current of the transistor Q₅₁ flows separately throughthe emitter of Q₅₁ and the collector of the transistor Q₅₃. Therefore,the base current of the transistor Q₅₂ decreases and the base current ofthe transistor Q₅₃ also decreases, so that high switching speed of thetransistor Q₅₃ is attained.

When at least one of the address signal leads A₀, A₁, A₂, A₃, A₄, or A₅is "low", the multi-emitter transistor Q₅₀ turns on and the collectorvoltage of the transistor Q₅₀ becomes low, so that the transistor Q₅₁,and therefore the transistors Q₅₂ and Q₅₃, all turn off. Therefore, thevoltage of the collector of the transistor Q₅₃ connected to the wordline W₀ goes "high", which means that the word line W₀ is not selected.

FIG. 6 illustrates the writing-in circuit unit or the program circuitunit for one bit line as used in the PROM embodiment described above. Inthe 4 K PROM device, 64 writing-in circuit units are used. Thewriting-in circuit unit in FIG. 6 comprises a PNP type transistor Q₆₀,an NPN type transistor Q₆₁, and a series connected resistor R₆₀ andzener diode ZD. The collector electrode of the transistor Q₆₀ isconnected to the output terminal T₁ of the bit address decoder G'₁ ofFIG. 3 and to the base electrode of the transistor Q₆₁. The emitterelectrode of the transistor Q₆₀ is connected to the output terminal T₅of the output buffer 16 of FIG. 3. The base electrode of the transistorQ₆₀ is connected to collector electrode of the transistor Q₆₁ and to theseries connected resistor R₆₀ and zener diode ZD, which has, forexample, a zener voltage of about 20. The emitter electrode of thetransistor Q₆₁ is connected to the terminal T₃ connected to a bit lineB_(i).

Operation of the circuit of FIG. 6 will now be described. Assume that ahigh voltage writing-in current of a constant current, for example 25V-120 mA, is supplied through the output terminal T₅ to the emitterelectrode of the transistor Q₆₀. A base current flows from the baseelectrode of the transistor Q₆₀ to the series connected resistor R₆₀ andzener diode ZD, and the PNP type transistor Q₆₀ turns on. In this state,if the voltage level of the output terminal T₁ of the decoder G'₁ is"high" (selected condition), current flows from the collector electrodeof the transistor Q₆₀ to the base electrode of the transistor Q₆₁, sothat the transistor Q₆₁ turns on.

When transistors Q₆₀ and Q₆₁ so turn on, the writing-in current passesfrom the output terminal T₅ through the transistors Q₆₀ and Q₆₁ and theterminal T₃ to the selected bit line B_(i).

In the circuit of FIG. 6, the series connection of the resistor R₆₀ andthe zener diode ZD constitutes a voltage control circuit which causestransistor Q₆₀ to turn off in the reading out mode, so that no currentflows from the output terminal T₅ through the writing-in circuit.

FIG. 7 illustrates the multiplexer unit and the output buffer unit usedin the preferred embodiment of the PROM device described above. In FIG.7, input terminals T₂₀₀ through T₂₁₅ of the multiplexer unit or thereading-out circuit unit are connected respectively to the baseelectrodes of 16 NPN transistors Q₇₀₀ through Q₇₁₅, the collectorelectrodes of which are connected commonly to the voltage source V_(cc)through resistor R₇₁, and the emitter electrodes of which are connectedcommonly to the base electrode of NPN transistor Q₇₁₆. Each baseelectrode of the transistors Q₇₀₀ through Q₇₁₅ is connected to the anodeelectrode of one of the diodes D₇₀₀ through D₇₁₅, and each cathodeelectrode of the diodes D₇₀₀ through D₇₁₅ is connected to one of the bitline terminals T₄₀₀ through T₄₁₅, respectively, which are connected tothe bit lines of the memory cell array. Each base electrode of thetransistors Q₇₀₀ through Q₇₁₅ is connected to the voltage source V_(cc)through one of resistors R₇₀₀ through R₇₁₅, respectively. The collectorelectrode of the transistor Q₇₁₆ is connected to the base electrode ofNPN transistor Q₇₁₇, and to the voltage source V_(cc) through resistorR₇₃. The emitter electrode of the transistor Q₇₁₆ is connected to thebase electrode of NPN transistor Q₇₁₈, and to the ground throughresistor R₇₅. The base electrode and the emitter electrode of thetransistor Q₇₁₆ are connected to each other through resistor R₇₂. Thecollector electrode of the transistor Q₇₁₇ is connected to the voltagesource V_(cc) through resistor R₇₄. The collector electrode of thetransistor Q₇₁₈ is connected to the output terminal T₅, and to theemitter electrode of the transistor Q₇₁₇ through diode D₇₃. The emitterelectrode of the transistor Q₇₁₈ is connected to the ground. The outputterminal T₅ is also connected to the current input terminal of thewriting-in circuit 20 of FIG. 3. The base electrodes of the transistorsQ₇₁₆ and Q₇₁₇ are connected to a common output terminal of inverter INV₅through diodes D₇₁ and D₇₂ respectively. In the 4 K-bit PROM device,four multiplexer units and four output buffer units are used, and onequarter of them is shown in FIG. 7.

Operation of the circuit of FIG. 7 will now be described. Assume thatthe level of the input terminal T₂₀₀ which is connected to the outputterminal of the bit address decoder is "high", and the level of the bitline terminal T₄₀₀ is "high", which means that the memory celltransistor Q_(c) connected between the selected word line and the bitline, which is connected to the terminal T₄₀₀, is not short-circuited.In this condition, the base electrode of the transistor Q₇₀₀ becomes"high", the transistor Q₇₀₀ turns on, and the transistor Q₇₁₆ turns on.In response to the turn-on of the transistor Q₇₁₆, the transistor Q₇₁₈turns on and the transistor Q₇₁₇ turns off; thereby the level of theoutput terminal T₅ becomes "low".

If the selected memory cell Q_(c) is short-circuited at its emitter-basejunction, the level of the base electrode of the transistor Q₇₀₀ is"low", and the transistor Q₇₀₀ turns off. In this case, the othertransistors Q₇₀₁ through Q₇₁₅, which are connected parallel to thetransistor Q₇₀₀, are also turned off because the other input terminalsT₂₀₁ through T₂₁₅ have been pulled down to a "low" level by non-selectedbit address decoders. Therefore, the transistor Q₇₁₆ turns off, thetransistor Q₇₁₈ turns off, and the transistor Q₇₁₇ turns on, so that thelevel of the output terminal T₅ goes "high".

In the above, the operation of the reading-out circuit in thereading-out mode was described. In the writing-in mode, the chip enablesignal CE is caused to become "high", and the output level of theinverter INV₅ goes "low"; thereby, the transistors Q₇₁₆, Q₇₁₇, and Q₇₁₈are all turned off. In such a state, the writing-in current of a highvoltage is supplied to the output terminal T₅ and the writing-inoperation is effected as described with reference to FIG. 6. However,the transistors Q₇₁₇ and Q₇₁₈ do not suffer breakdown because thesetransistors are in a cut-off state.

FIG. 8 illustrates another embodiment of the present invention. In FIG.8, the bit address buffer unit BB'₆ is composed of two inverters INV₆and INV₇ connected in series, the output terminals of which areconnected to the address signal lines 24 of the writing-in stage and theaddress signal lines 26 of the reading-out stage. The other circuits arethe same as the circuits explained with reference to FIG. 3. In theprior art PROM device illustrated in FIG. 2, the address signals to thewriting-in stage and the address signals to the reading-out stage aresupplied from different inverters, in order not to decrease theoperating speed of the reading-out stage. However, in this embodiment ofthe present invention, it is possible to omit two inverters and tosupply the bit address signals to the writing-in stage and thereading-out stage from common inverters, as shown in FIG. 8, so that thebit address buffer circuits can be greatly simplified and the packingdensity of the PROM device can be increased. This is because thecurrent, that flows from the program circuit 20 through the bit addressdecoder 12 to the bit address inverters can be very small according tothe present invention.

In the above description, a PROM device having shorted-junction typememory cells is explained. However, it should be noted that the presentinvention can be adapted to other types of PROM devices, for example, toa bipolar PROM device having fuse-blown type memory cells.

It is preferable to adapt the present invention to a PROM device,including Schottky TTL gates, which can be formed without gold doping ofthe substrate of the device. In such a PROM device, the PNP typetransistors of the bit address decoders can be formed as so-called"vertical PNP type transistors".

What is claimed is:
 1. A bipolar PROM device having a plurality ofmemory cells which are located at respective cross positions of aplurality of word lines and a plurality of bit lines and which areselected by word address signals and bit address signals applied to saidPROM device, said PROM device comprising:a word address buffer foramplifying said word address signals; a word address decoder fordecoding the word address signals from said word address buffer; one ormore bit address buffers for amplifying said bit address signals; afirst bit address decoder for decoding the bit address signals from saidbit address buffer for writing-in of information; a second bit addressdecoder for decoding the bit address signals from said one or more bitaddress buffers for reading-out of information, at least one of saidfirst and second bit address decoders being composed of a plurality ofAND gates, each of said AND gates comprising an output terminal and aplurality of PNP type transistors each comprising an emitter, a base,and a collector, to each said base of said transistors being applied theaddress signals from said bit address buffer, each said collector ofsaid transistors being connected commonly to ground, and each saidemitter of said transistor being connected commonly to said outputterminal of said AND gate; a program circuit for initially writing-ininformation to the selected memory cells; and a multiplexer forreading-out information from the selected memory cells.
 2. A bipolarPROM device as set forth in claim 1, wherein said bit address signalsare supplied to said first and second bit address decoders from a singlecommon bit address buffer.
 3. A bipolar PROM device as set forth inclaim 2, wherein said common bit address buffer is composed of aplurality of pairs of series connected inverters.
 4. A bipolar PROMdevice as set forth in claim 1, wherein said bit address signals aresupplied to said first and second bit address decoders through addresssignal lines.
 5. A bipolar PROM device as set forth in claim 1, whereinsaid first bit address decoder comprises output terminals which areconnected to input terminals of said program circuit.
 6. A bipolar PROMdevice as set forth in claim 1, wherein said second bit address decodercomprises output terminals which are connected to input terminals ofsaid multiplexer.
 7. A bipolar PROM device as set forth in claim 1,wherein each of said plurality of memory cells consists of an open basetype transistor connected between one of said plurality of bit lines andone of said plurality of word lines
 8. A bipolar PROM device as setforth in claim 1, wherein said PNP transistors comprise verticaltransistors.
 9. A bipolar PROM device as set forth in claim 1,whereinsaid bit address signals are supplied to said first and second bitaddress decoders and wherein each of said bit address buffers comprisesfirst, second, third, and fourth inverters connected in series, saidfirst and second inverters of each respective bit address buffer beingconnected to said second bit address decoder, and said third and fourthinverters being connected to said first bit address decoder.